Cadence Academic Network
The academic network was launched in 2007 by Cadence Europe. The aim was to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected European universities, research institutes, industry advisors and Cadence was established to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic systems.
At the Institute of Electrical and Optical Communications Engineering Cadence software is an important component in education. It is utilized in various extents: from a workshop over a lab course up to a thesis.
A two-afternoon-workshop is offered within the scope of the lecture “Physical Design of Integrated Circuits”. It is intended to give the students a first introduction into the Cadence-World. During the first afternoon the participants will be aquainted with the Cadence framework, the Virtuoso Schematic Editing Window and with various simulation techniques. In the second part the students will work with the Virtuoso Layout Editor. They will create their own layout and extract parasitics from it. Furthermore the students will compare their layout design with the schematic design they created during the first part, by both doing a layout-versus-schematic check and by doing some re-simulations and comparing them to the schematic simulations to study the impact of the parasitics.
- Lab Course
The lab courses „Entwurf integrierter Schaltungen” (german) and „Physical Design of Integrated Mixed-Signal Circuits” introduce Cadence's development tools to students. At the beginning simple circuits which are made from scrach are investigated using transient, dc and ac analysis.
Theoretical basics of amplifiers like their transfer characteristic, non-linearity or noise are visualized by means of transient, dc, ac, noise and pss (periodic steady state) analysis. The Cadence Virtuoso Schematic Editor and Cadence Spectre are applied for the design or the simulation of circuits, respectively.
Layouts of circuits are drawn with Cadence Virtuoso Layout Editor and DRCs (design rule checks) are performed in order to eliminate violations of the design rules. Furthermore the topoligies of all layouts have to match the corresponding schematics which is assured by LVS (layout-versus-schematic) checks.
Students can make all kinds of bachelor- and master thesis at the institute. Possible topics cover the development of new circuits, partial circuits for large projects and the redesign of circuits.
The practical part of the workshop, the lab course and the thesis takes place at our CAD-Lab. It provides a powerful client-server-infrastructure and the latest design software. In the thesis current research topics are discussed. Our students work with leading-edge design kits of famous semiconductor manufacturers.
Contact personDr.-Ing. Thomas Veigel
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